1. Field of the Invention
The present invention relates to a semiconductor memory device and a write method thereof, and the invention is applied, for example, to a NAND flash memory.
2. Description of the Related Art
Conventionally, for example, in a NAND flash memory, there is a variance in write characteristics between memory cells due to shapes of processed memory cells in a fabrication process or due to a thermal process in fabrication. In a read operation of the NAND flash memory, a pass potential (Vpass) is also delivered to cells, which are not selected for data read, in a selected NAND string. Thus, even if there is such a variance in characteristics, it is necessary to execute precise control to set a write voltage (Vpgm) for all cells at a level lower than a read voltage (Vread).
Normally, in the NAND flash memory, in order to suppress the variance in write characteristics, a verify write operation is executed for each of memory cells (i.e. for each bit). In the verify write, after a write operation is performed, a verify read operation is first executed to determine whether a predetermined threshold value Vth is reached or not with respect to each memory cell (each bit). Subsequently, as regards only the memory cell which has been determined to be in a “deficient write” state by the verify read operation, verify write is executed once again. The verify write is executed by increasing, by a predetermined value, the voltage of a write pulse in a preceding verify write operation (step-up write).
In the verify read, a pass potential is delivered to a non-selected cell, and a determination potential is delivered to a selected cell. As a result, when a predetermined cell current flows, the data that is written in the memory cell is determined to be, for example, “0”.
A cell current at this time is affected by various parasitic resistances, such as an internal resistance in a peripheral circuit, a bit line resistance, a bit line contact resistance, a diffusion layer resistance of a NAND string, a channel resistance of a non-selected cell, a source line contact resistance, and a source line resistance. Of these factors, the influence of source line noise, which occurs due to the source line parasitic resistance, is large.
The source line noise occurs due to a variation in electric current flowing in the source line. As regards the source line noise, when one page is accessed, the cell current varies in accordance with the variation in threshold voltage of the cell. Thus, the magnitude of cell current varies depending on the pattern of the threshold voltage Vth of neighboring cells. Accordingly, if the threshold voltage Vth of the neighboring cell varies, the read-out threshold voltage Vth of the cell also varies.
The influence of the source line noise conspicuously occurs at the initial stage of data write, that is, when verify read of a fast-write cell, in which data write is executed fast, is executed in the state in which the threshold voltage Vth of a late-write cell, for which data write is executed late, is still low (i.e. the cell current is large). In this case, at the time of the verify read, the potential drop of the source line is large, and the threshold voltage Vth of the cell is determined in the state in which the threshold voltage Vth appears to be high. Consequently, the cell is erroneously determined to meet the verify voltage.
On the other hand, when the write operation is close to the end, the threshold voltages of all cells in the page become close to predetermined threshold voltages. Thus, the potential drop of the source line decreases, the influence of the source line noise is small, and the verify voltage is close and the threshold voltage of each cell is determined. In the case of such a write operation, the above-mentioned erroneously determined cell (the fast-write cell) fails to meet the verify voltage. As a result, the threshold voltage that is set in the cell becomes lower than the predetermined threshold voltage, and the read margin decreases.
A publicly known document relating to the invention of the present application is Jpn. Pat. Appln. KOKAI Publication No. 2000-48582. Jpn. Pat. Appln. KOKAI Publication No. 2000-48582 discloses a semiconductor memory device relating to prevention of defective write due to rising of the potential of the common source line of memory cells.